Generally, a semiconductor device includes interconnect structures electrically connecting active devices (e.g., transistors or capacitors) to create functional circuits. These interconnect structures include conductive features (e.g., metal lines and vias) formed in various dielectric layers. The formation of conductive features (e.g., metal lines and vias) in a dielectric layer generally involves patterning the dielectric layer to form trenches and filling the trenches with a conductive material.
Typically, trench formation is done using a combination of photolithography and etching. A hard mask may be disposed over a dielectric layer as a patterning mask for etching the dielectric layer. As the desired critical dimensions (e.g., width of trenches and/or the spacing between trenches) become smaller and smaller in advanced semiconductor devices, traditional methods for patterning hard masks and dielectric layers may result in large overhangs on sidewalls of a trench and other issues. These defects may negatively affect yield, subsequent trench filling processes, and leakage control issues.